isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 1 of 9 gate driver for si c sjt with output and signal isolation features product image ? requires single 12 v voltage supply ? pin out compatible with mosfet driver boards ? multiple internal level topology for low drive losses ? high-side drive capable with 3000 v isolation ? 5000 v signal isolation (up to 10 s) ? capable of high gate currents with 3 w maximum power ? rohs compliant section i: introduction the GA03IDDJT30-FR4 prov ides an optimized gate drive solution for sic juncti on transistors (sjt). t he board utilizes dc/dc conv erters and fod3182 opto-isolators making it capable of driving high and low-side devices in a half-bridge configuration as well as ixd n609 gate driver ics providing fast switching and cu stomizable continuous gate currents necessary for sjt devices. its footprint and 12 v supply voltage make it a plug-in replacement for exis ting sic mosfet gate drive solutions. figure 1: simplified GA03IDDJT30-FR4 gate drive board block diagram section ii: compatibility with sic sjts the GA03IDDJT30-FR4 has an installed r g of 3.75 ? on-board which may need to be modified by th e user for safe operation of certain sjt parts. please see the table below and se ction vii for more information. table 1: GA03IDDJT30-FR4 ? sic sjt compatibility information table sjt part number compatible requires r g modification ga03jt12-247 yes not required ga05jt12-247/263 not required ga06jt12-247 not required ga10jt12-247/263 recommended (see section vii) ga20jt12-247/263 required (see section vii) ga50jt12-247 required (see section vii) ga04jt17-247 not required ga16jt17-247 required (see section vii) ga50jt17-247 required (see section vii) v isolation = 3000 v p drive = 5 w f max = 350 khz
isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 2 of 9 section iii: operational characteristics section iv: pin out description figure 2: gate drive board top view table 2: GA03IDDJT30-FR4 pin out connections header pin label suggested connection jp1 vcc high + 12 v, > 6 w supply jp1 vcc high rtn a nalog ground jp1 signal gate drive control signal jp1 signal rtn a nalog ground jp1 vcc low + 12 v, > 6 w supply jp1 vcc low rtn a nalog ground gate gate sjt gate pin gate gate sjt gate pin gate gate sjt gate pin source source sjt source pin source source sjt source pin source source sjt source pin parameter symbol conditions value unit notes min. typical max. input supply voltage v cc v cc high, v cc low 10.8 12 13.2 v input signal voltage, off v sig, off -5 0 0.8 v input signal voltage, on v sig, on 3.2 5.0 6.4 v input signal current, on i si g , on 20 36 50 ma propagation delay, signal turn on t d,on 160 270 ns propagation delay, signal turn off t d,off 187 270 ns output gate current, peak i g,on 4 9.0 a output gate current, continuous i g,steady d = 0.3, f < 350 khz 0.35 1.8 a output gate voltage rise time t r c load = 10 nf 21 35 ns output gate voltage fall time t f c load = 10 nf 14 25 ns operating frequency f sw dependant on device driven and c g 350 khz power dissipation p tot 3.0 w (v gl ) + 2.0 w (v gh + v ee ) 5.0 w sjt drain ? source voltage v ds on driven power transistor 1700 v isolation voltage, signal v iso-sig 5000 v isolation voltage, voltage supply v iso-dc 3000 v storage temperature t -55 100 c product weight 19 g source source source gate gate gate vcc low rtn vcc low signal rtn signal vcc high rtn vcc high
isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 3 of 9 section v: sjt gate driving theory of operation the sjt transistor is a current controlled transistor which requires a positive gate curr ent for turn-on as well as to remain i n on-state. an ideal gate current waveform for ultra-fast switching of the sjt, while maintaining low gate drive losses, is shown in figure 3. this is similar to what the GA03IDDJT30-FR4 provides. an sjt is rapidly switched on when the necessary gate charge, q g , for turn-on is supplied by a burst of high gate current, i g,on , until the gate- source capacitance, c gs , and gate-drain capacitance, c gd , are fully charged. , the i g,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-state. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the device package and drive circuit. a voltage developed across the parasit ic inductance in the source path, l s , can de-bias the gate-source junction, when high drain currents begin to flow through the device. the applied gate voltage should be maintained high enough, above the v gs,on level to counter these effects. after the sjt is turned on, i g may be lowered to i g,steady for reducing unnecessary gate drive power losses. the minimum i g,steady is determined by noting the dc current gain, h fe , of the device from its datasheet. the desired i g,steady is determined by the peak device junction temperature t j during operation, drain current i d , dc current gain h fe , and a 50 % safety margin to ensure operating the device in the saturation region with low on-state voltage drop by the equation: , , 1.5 for sjt turn -off, a high negative peak current, -i g,off at the start of the turn-off transition rapidly sweeps out charge from the gate. while satisfactory turn off can be achieved with v gs = 0 v, a negative gate voltage v gs may be used in order to speed up the turn-off transition. the GA03IDDJT30-FR4 provides a negative bias of -5 v during off state. figure 3: idealized sjt gate current waveform
isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 4 of 9 section vi: gate driver implementation the GA03IDDJT30-FR4 is a gate driver circ uit which can be used to drive an sjt transis tor by supplying the required gate drive current i g in a low-power gate drive solution. this conf iguration features a gate capacitor c g (cg1 and cg2 in parallel) which creates a brief current peak i g,on during device turn-on and i g,off during turn-off for fast switching and a gate resistor r g (rg1 and rg2 in parallel) to set the continuous gate current i g,steady required for an sjt to operate. this conf iguration is shown in the fi gure 7 circuit diagram as well as in figure 4 below with further details provided below. this secti on provides detail on selecting optimal c g and r g values based on the sjt, drain current, and temperature. figure 4: primary gate drive circuit passive components with series gate resistance schottky rectifier. table 3: passive output component list symbol parameter values range default units r g gate resistor, on board 0 ? 20 3.75 ? c g gate capacitor, on board 5 ? 20 10 nf r 4 charging resistor 500 ? 10k 1k ? d 1 schottky diode of gate resistor -- -- a: gate resistor r g modification the GA03IDDJT30-FR4 on board gate resistor r g controls the continuous current i g,steady during steady on-state. the gate current is determined according to: , , 0.6? , 4.7 , 0.6? where v gl is the internal, low-level drive voltage (5 v), v gs,sat is the driven sjt saturated gate-sour ce voltage obtained from the individual device datasheets, v d is the schottky diode voltage drop (approximately 0.3 v), and 0.6 ? is added from internal GA03IDDJT30-FR4 drive components. it is necessary for the user to reduce r g from its pre-install value of 3.75 ? for several sic sjts for safe operation with the ga03iddjt30- fr4 under high drain current conditions. the location of rg on t he circuit board is shown in figure 5. the maximum allowable va lue of r g for each device across all rated drain currents can be found in t he gate drive section of each individual device datasheets. r g may also be calculated from the following equation, where h fe is the sjt dc current gain and v gs,sat is the gate-source saturation voltage. both of these values may be taken from individual device datasheets. , 4.7 , , 1.5 0.6 for some devices and drain currents it may be desir ed for the user to install a very low value of r g or to short r g (r g = 0 ? ) to increase the gate current output. this is acceptable, but may limit the duty cycle d during operation. please s ee section vii:b for more inf ormation. b: duty cycle limitation the duty cycle d of the GA03IDDJT30-FR4 output may be limited by the 3 w power capability of the internal 5 v supply in some applications. if r g remains un-changed by the user i g,steady will remain sufficiently low to allow 100 % duty cycle operation with an sjt. however, if r g is shorted or reduced such that r g 2.8 ? in order to drive higher current devices, the duty cycle will be limited by the following equation: 3 5 , 0.9
isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 5 of 9 figure 5: location of r g (rg1 and rg2 in parallel) on GA03IDDJT30-FR4 driver for substitution c: gate capacitor c g modification an external gate capacitor c g connected directly to the device gate pin delivers the positive current peak i g,on during device turn-on and the negative current peak i g,off during turn-off. a high value resistor r 4 in parallel with c g sets the sjt gate pin to a defined potential (-v ee ) during steady off-state. at device turn-on, c g is pulled to the GA03IDDJT30-FR4 internal voltage level v gh which produces a transient peak of gate voltage and current. this current peak rapidl y charges the internal sjt c gs and c gd capacitances. a schottky diode, d1, in series with r g blocks any c g induced current from draining out through r g and ensures that all of the charge within c g flows only into the device gate, allowing for an ultra- fast device turn-on. during steady on-state, a potential of v gh - v gs = v gh ? 3 v is across c g . when the device is turned off, c g is pulled to negative v ee and v gs is pulled to a transient peak of v gs,turn-off = v ee ? (v gh ? 3 v), this induces the negative current peak i g,off out of the gate which discharges the sjt internal capacitances. d: voltage supply selection the GA03IDDJT30-FR4 gate drive design feat ures three internal supply voltages v gh , v gl , and v ee (listed in table 4) supplied through two dc/dc converters. during device turn-on, v gh charges the capacitor c g thereby delivering the narrow width, high current pulse i g,on to the sjt gate and charges the sjt?s inter nal terminal capacitances c gd and c gs . for a given level of parasitic i nductance in the gate circuit and sjt package, the rise time of i g,on is controlled by the value of v gh and c g. during the steady on-state, v gl in combination with the internal and external gate resistances provid es a continuous gate current for the sjt to remain on. the v ee supply controls the gate negative voltage during turn-off and steady off-state for faster switching and to av oid spurious turn-on which may be caused by external circuit noise. the power rating of the provided voltage supplies are adequate to meet the gate drive power requirements as determined by , 1 2 , 1 2 , , table 4: GA03IDDJT30-FR4 gate drive voltage supply component list symbol parameter values range default v gh supply voltage, gate capacitor 15 ? 20 + 20.0 v gl supply voltage, gate resistor 5.0 ? 7.0 + 5.0 v ee negative supply voltage -10 ? gnd - 5.0 e: voltage supply isolation the dc/dc supply voltage converters are suggested to prov ide isolation at a minimu m of twice the working v ds on the sjt transistor during off-state to provide adequate protection to ci rcuitry external to the gate drive circ uit. the installed dc/dc converters have a n isolation of 3.0 kv and greater. alternatively, dc/dc c onverter galvanic isolation may be bypass ed and direct connection of variable voltage supplies may
isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 6 of 9 be done in a laboratory environment, this may be convenient duri ng testing and prototyping but carries risk and is not suggeste d for extended usage. figure 6: typical dc/dc converter configuration f: signal isolation the gate supply signal is suggested to be isolated to twice the working v ds on the sjt during off-state to provide adequate protection to circuitry external to the gate driv e circuit. this may be done using opto or galvanic isolation techniques.
isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 7 of 9 section vii: detailed schematic and bill of materials figure 7: gate drive board detailed block diagram table 5: gate drive board bill of materials #item designator description package (metric) manufacturer manufacturer part number quantity / board 1 c1, c2, c3, c4, c5 capacitor, ceramic, 1f, 50v, 10%, x7r, 1206 3216 tdk corporation c3216x7r1h105k160ab 5 2 cg1, cg2 capacitor, ceramic, 4700pf, 250vac, x7r, 1812 4532 murata electronics na ga343dr7gd472kw01l 2 3 c6, c7, c9 capacitor, ceramic, 0.1f, 50v, 10%, x7r, 1206 3216 yageo cc1206krx7r9bb104 3 4 c10 capacitor, ceramic, 22f, 35v, 20%, x5r, 1206 3216 tdk corporation c3216x5r1v226m160ac 1 5 c8 capacitor, ceramic, 100f, 16v, 20%, x5r, 1210 3225 taiyo yuden emk325abj107mm-t 1 6 r2, r3 resistor, 10 ? , 1/4w, 1%, 1206, smd 3216 rohm semiconductor mcr18ertf10r0 2 7 r1 resistor, 100 ? , 1/4w, 1%, 1206, smd 3216 yageo rc1206fr-07100rl 1 8 r4 resistor, 1 k ? , 1/4w, 1%, 1206, smd 3216 yageo rc1206fr-071kl 1 9 rg1, rg2 resistor, 7.50 ? , 1w, 1%, 2512, smd 6332 vishay dale crcw25127r50fkeg 2 10 d1 schottky diode, 60v, 2a, smb smb fairchild semiconductor ss26 1 11 u1, u2 optocoupler, 3a, 8-smd 8-smd fairchild semiconductor fod3182s 2 12 gate, source connector breakaway, header 0.100in, 3pos, vertical 3pos header te connectivity 5-146274-3 2 13 jp1 connector breakaway, header 0.100in, 6pos, vertical 6pos header te connectivity 3-644456-6 1 14 u3 dc/dc converter, 3w, v in = 12v, v o = 5v, 7-sip 7-sip module murata power mev3s1205sc 1 15 u4 dc/dc converter, 2w, v in = 12v, v o = 20/- 5v dual, 7-sip 7-sip module murata power mgj2d122005sc 1 16 u5, u6 gate driver ic, 9a, non- inverting, 8-soic 8-soic ixys ic ixdn609si 2 17 -- gate driver circuit board, 0.062? thickness, 4oz cu pcb genesic semiconductor GA03IDDJT30-FR4 1 i g cg2 sic sjt gate signal v gh d1 r4 r1 u1 v gl v ee u2 v gl v ee v gl u3 v gh u4 v ee c2 c1 v ee u5 v gl v ee u6 cg1 rg1 rg2 r2 r3 c5 c3 c4 c8 c6 c9 c10 +12 v +12 v vcc high vcc high rtn vcc low vcc low rtn signal signal rtn gate source voltage isolation barrier GA03IDDJT30-FR4 gate driver board d s g
isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 8 of 9 section viii: mechanical drawing figure 8: gate drive board mechanical drawing
isolated gate driver GA03IDDJT30-FR4 nov. 2014 http://www.genesicsemi.com/commerc ial-sic/sic-junction-transistors/ pg 9 of 9 revision history date revision comments supersedes 2014/11/14 1 updated characteristics 2014/08/29 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specificat ions and data in this document without noti ce. genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or i mplied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic cont rol and weapons systems, nor in applications where their failure may result in death , personal injury and/or property damage.
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